In Active Matrix Display, scan lines of respective rows and data lines of respective columns intersect to constitute an active matrix. A progressive scanning method is usually adopted to turn on transistors of respective rows sequentially and write voltage on data lines into pixels. A row scanning and driving circuit integrated on a display back board has the advantages of narrow edge and low cost, and has been used in most of LCD/AMOLED display devices.
There are many kinds of processes for manufacturing a back board of display devices at present, for example, a-Si, LTPS, Oxide Thin Film Transistor(TFT), and etc. The a-Si process is relative mature and has low cost, but a-Si TFT has the disadvantages of low mobility and low stability. LTPS TFT has the advantages of rapid speed and great stability and the disadvantages of low uniformity and high cost, and is not suitable to the preparation of a panel with large size. Oxide TFT has the advantages of high mobility, good uniformity and low cost, and is a kind of technology of best suitable to a large size panel in future. However, the I-V transfer characteristics of the Oxide TFT is usually in a depletion mode, that is, the Oxide TFT is still turned on when a gate-source voltage Vgs of the Oxide TFT is zero.
A depletion type TFT brings challenge on the integration of a shift register on a display back board. FIG. 1A is a structure diagram of a conventional shift register, and all of transistors in FIG. 1A are N-type TFTs. As shown in FIG. 1A, the conventional shift register includes a first output transistor T1, a second output transistor T2, a first control module 11 for controlling T1 and a second control module 12 for controlling T2. An output terminal of a shift register at each stage is connected to an input terminal of a shift register at a next stage, and shift registers at respective stages are controlled alternately by two clock signals CLK1 and CLK2 having a duty ratio of 50%. All of input signals and control signals have a swing of VGL˜VGH, wherein VGL is a low level and VGH is a high level. The first output transistor T1 is connected to the clock signal CLK2 and the output terminal OUT(n) and functions as transferring the high level, and the second output transistor T2 is connected to a low level output terminal for outputting the low level VGL and the output terminal OUT(n) and functions as transferring the low level.
As shown in FIG. 1B, operations of the shift register can be divided into three phases:
A first phase is a pre-charging phase, when an output terminal OUT(n−1) of a shift register at a previous stage generates a high level pulse, a PU node (a node connected to a gate of T1, that is, a pulling-up node) is controlled to be charged to the high level VGH, and meanwhile a PD node (a node connected to a gate of T2, that is, a pulling-down node) is controlled to be discharged to the low level VGL, so that T1 is turned on to transfer the low level of CLK2 to the output terminal OUT(n) and T2 is turned off;
A second phase is an evaluating phase, in a next half clock cycle, the PU node becomes a floating state, that is, no signal is input to the PU node since transistors of the first output control module connected thereto are all turned off; CLK2 becomes the high level from the low level, as an output voltage increases, an voltage at the PU node is bootstrapped to a higher level by a capacitor connected between the gate of T1 and the output terminal OUT(n), so that it is ensured that there is no threshold loss in the output voltage at the output terminal OUT(n), and the PD node keeps at the low level to maintain T2 off and in turn it avoids the electric leakage of the high level outputted at the output terminal OUT(n) through T2; and
A third phase is a resetting phase, in a third half clock cycle, CLK2 becomes the low level and CLK1 becomes the high level, the PU node is discharged to the low level and the PD node is recharged to the high level, T1 is turned off and T2 is turned on at this time, so that the output voltage at the output terminal OUT(n) becomes the low level via T2.
It can be known from FIG. 1B, the PU node and the PD node have an opposite relationship, so that it is avoided that T1 and T2 are turned on simultaneously to cause abnormal output.
However, if T1 and T2 in FIG. 1A are depletion type transistors, a large distortion occurs in the output voltage. First, in the evaluating phase, the voltage at PU node is at the high level and thus T1 is turned on, on the other hand, T2 cannot be turned off normally but generates a leakage current due to the depletion characteristics of T2 although the gate-source voltage Vgs of T2 is zero since the voltage at the PD node is discharged to the low level VGL, that is, T1 and T2 are turned on simultaneously, and thus the potential of the output voltage outputted at the output terminal depends on the voltage division of T1 and T2 and is usually lower than the normal high voltage too much, which in turn affects normal operations of a shift register at a next stage and may cause malfunction of next stages. Secondly, in the resetting phase, the voltage at the PU node is at the low level and the voltage at the PD node is at the high level, and the output voltage at the output terminal OUT(n) is at the low level; at the same time, T1 is continually turned on as it is the depletion type transistor, and the output voltage at the output terminal OUT(n) would generate a high level pulse and the potential thereof depends on the voltage division of T1 and T2 when CLK2 becomes the high level. A normal waveform of the output voltage at the output terminal OUT(n) is shown by a liquid line in FIG. 1C, and a distorted waveform of the output voltage at the output terminal OUT(n) is shown by a dotted line in FIG. 1C.
Besides the first output transistor T1 and the second output transistor T2, other depletion type TFTs in the internal control circuit would cause abnormal output as well. As shown in FIG. 2A, the second control module is a pulling-down transistor control module, and the first control module includes T3 and T4 which are depletion type transistors, wherein T3 is connected to the output terminal OUT(n−1) of the shift register at a previous stage and the PU node (the node connected to the gate of T1) and functions to charge the voltage at the PU node to the high level in the pre-charging phase; T4 has a gate connected to a reset signal Rst and is connected between the PU node and the low level output terminal for outputting the low level VGL, and functions to pull down the voltage at the PU node in the resetting phase. The depletion type transistors T3 and T4 are turned on in the evaluating phase, the voltage at the PU node is pulled down, so that T1 is not turned on completely, which affects the potential of the output voltage at the output terminal OUT(n), as shown by a dotted line in FIG. 2B.
Therefore, there is a need for improving the circuit structure of the shift register to remove the effect of the depletion type TFT on the output voltage of the shift register.